1. Technical Field
The present disclosure relates to a control device for rectifiers of switching converters.
2. Description of the Related Art
Resonant converters are a large class of forced switching converters characterized by the presence of a half-bridge or a full-bridge circuit. In the half-bridge version, for example, the switching elements comprise a high-side transistor and a low-side transistor connected in series between an input voltage and ground. A square wave having a high value corresponding to the power supply voltage and a low value corresponding to ground may be generated by conveniently switching the two transistors.
The square wave generated by the half-bridge is applied to the primary winding of a transformer by means of a resonant network which comprises at least one capacitor and one inductor. The secondary winding of the transformer is connected with a rectifier circuit and to a filter to provide an output direct voltage depending on the frequency of the square wave.
At present, one of the resonant converters most widely used is the LLC resonant converter. This name derives from the fact that the resonant circuit employs two inductors (L) and a capacitor (C). A schematic circuit of an LLC resonant converter is shown in FIG. 1 and comprises a half-bridge of MOSFET transistors Q1 and Q2, with respective body diodes Db1 and Db2, between an input voltage Vin and ground GND and driving by a driver circuit 3. The common terminal between transistors Q1 and Q2 is connected to a resonant network 2 comprising a series of a first inductance Lr, a second inductance Lm and a capacitor Cr; the inductance Lm is connected i in parallel to a transformer 10 comprising a secondary winding L2. The last is normally connected to the parallel of a capacitor Co and a resistance Rout by means of the rectifier diodes.
These resonant converters are characterized by a high conversion efficiency (>95% is easily achievable), an ability to work at high frequencies, low generation of EMI (Electro-Magnetic Interference).
In current types of converter circuits, a high conversion efficiency and high power density are desired, as in the case, for example, of the AC-DC adaptors of notebooks. LLC resonant converters are at present the converters that best meet such desires.
However, the maximum efficiency achievable is limited by the losses in the rectifiers on the secondary side of the converter, which account for over 60% of total losses.
It is known that in order to significantly reduce the losses connected to secondary rectification, recourse can be made to the so-called “synchronous rectification” technique, in which rectifier diodes are replaced by power MOSFETs, with a suitably low on-resistance, such that the voltage drop across it is significantly lower than that across the diode; and they are driven in such a manner as to be functionally equivalent to the diode. This technique is widely adopted in traditional converters, especially in flyback and forward converters, for which there also exist commercially available dedicated integrated control circuits. There is an increasingly pressing desire to adopt this technique in resonant converters as well, in particular in LLC converters, in order to enhance their efficiency as much as possible.
FIG. 1 shows the converter wherein in the place of diodes there are two transistors SR1 and SR2, suitably driven by two signals G1 and G2 and connected between the terminals of the two parts of the center-tapped CT secondary winding connected to ground GND, while the parallel of Co and Rout is disposed between the center tap CT of the secondary winding L2 and ground GND. The output voltage Vout of the resonant converter is the voltage across said parallel, while the output current Io flows through the resistance Rout.
The transistors SR1 and SR2 have respective body diodes Dbr1 and Dbr2, and are both driven by a synchronous rectifier driver 4. The center-tap terminal of the secondary winding is then connected to the parallel of a capacitor Co and a resistance Rout. The output voltage Vout of the resonant converter is the voltage across said parallel, while the output current Io flows through the resistance Rout.
In operation, the transistors SR1 and SR2 are driven in such a manner to be alternatively turned-on by the synchronous rectifier driver 4. When the body diode Dbr1, Dbr2 of one of the transistors SR1, SR2 starts conducting the relative transistor is turned-on, while when the current is approaching to zero the transistor is turned-off; in this way the use of the transistors SR1, SR2 causes a lower voltage drop than the use of the rectifier diodes and the power dissipation is reduced.
Particularly, as is shown in FIG. 2, a phase A is activated when the voltage Vdvs between the drain and source terminals of one of the transistor SR1, SR2, for example SR1, is lower than a voltage value of 0.7V the relative body diode Dbr1 starts conducting; then when the voltage Vdvs falls under the on voltage threshold VTH_ON and after a fixed delay time period TPD_ON, always if the voltage Vdvs is maintained under the on voltage threshold VTH_ON, the transistor SR1 is turned on from the driver by the signal G1.
After the turn on of the transistor SR1, in a phase B, the voltage Vdvs has a value of Vdvs=−Rdson×Isr1, wherein Rdson is the on resistance of the transistor SR1, SR2 and Isr1 is the current flowing through the electric path between the center-tap CT of the secondary winding L2 of the transformer, the transistor SR1 and ground GND.
When the voltage Vdvs has a value higher than a second voltage threshold Vdsoff, the transistor SR1 is turned off by the driver. The respective body diode Dbr1 conducts again and the voltage Vdsv goes negative; when the voltage Vdsv reaches the value of 1.4V, the drive circuit relative to the transistor SR2 is enabled.
However, the voltage Vdvs depends on parasitic elements of the source and drain terminals of the transistor SR1, SR2 and of the path on a printed circuit board (PCB) from the drain terminal of the transistor SR1, SR2 to the terminal of the secondary winding L2. Particularly, the voltage Vdsv depends on the parasitic inductances Lsource and Ldrain associated to the source and drain terminals of the transistor SR1, SR2 and on the parasitic inductance Ltrace relative to the path on the printed circuit board (PCB) from the drain terminal of the transistor SR1, SR2 to the terminal of the secondary winding, therefore, indicating with Isr the current Isr1 or Isr2, the voltage Vdvs equals as follows:
      Vdvs    =                            -          Rdson                ×        Isr            -                        (                      Ldrain            +            Lsource            +            Ltrace                    )                ×                              ∂            Isr                                ∂            t                                ,that is the parasitic inductances make the sensed voltage Vdvs different from the ideal voltage drop value on Rdson.
The presence of the parasitic inductances Ldrain, Lsource and Ltrace determines an undesired earlier turn-off of the transistors SR1, SR2.
A known technique to avoid the earlier turn-off of the transistors SR1, SR2 is to compensate for the time advance due to the parasitic inductances by adding an RC filter. The RC filter comprises an external capacitor and a tunable resistor. Current inversion should be avoided to prevent converter malfunctions and failure.
The RC compensation of the parasitic inductances Ldrain, Lsource and Ltrace may cause a delay to turn on the transistors SR1, SR2; a bypass diode arranged in parallel to the tunable resistor eliminates this turn-on time delay. Furthermore, a resistor, of the value of about 100-200Ω, arranged in series to the bypass diode is typically used to limit current out of the drain terminal of the transistors SR1, SR2, in the case wherein the voltage Vdvs goes excessively under ground GND.
This solution has the advantages of providing a simple architecture with a consequent low cost in term of silicon area and good performance.
The driver 4 of the transistors SR1, SR2 provides a discharge path to ground GND for the gate terminals G1, G2 of the transistors SR1, SR2. For example, the prior art driver 4 allows the discharge of the gate terminal G1 through a discharge path comprising a low side transistor Mdl (an NMOS transistor) of a half-bridge the high side transistor Mdh (a PMOS transistor) of which is connected to the supply voltage Vcc (as shown in FIG. 3. Both the transistors Mdh, Mdl are driven by a pre-driver 5 connected to an internal supply voltage Vdd and having at the input the signal GD-ON. The transistor Mdl is turned on fast to allow a fast turn off of the transistor SR1 in order to avoid inversion current problems.
However, the on resistance Rondl of the low side transistor Mdl in combination with the parasitic gate-drain capacitance CGD of the MOS transistor SR1 and the parasitic inductances (the parasitic inductances Lbonding between the pin GD and the driver 4 and between the driver 4 and ground pin GND PIN, the inductance Lpcb from the ground pin GND PIN and the ground plane GND of the printed circuit board wherein the transistors SR1, SR2 are implemented, and the inductance Lgate between the pin GD and the gate terminal G1 of the MOS transistor SR1) form a high level of noise on internal ground plane GND and on the internal supply voltage Vdd, that is the ground and supply voltage nodes inside the integrated circuit wherein the control device 4 is implemented, due to the discharge path from the drain terminal of the MOS transistor SR1, SR2 to ground GND.
Also the parasitic gate-drain capacitance CGD of the MOS transistor SR1, SR2 form a current spike in the discharge path from the drain terminal of the MOS transistor SR1, SR2 to ground GND through the transistor Mdl.